IEEE

Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis

Abstract: We propose a novel transistor-level synthesis method to minimize the number of transistors needed to implement a digital circuit. In contrast with traditional standard cell design methods or ...
IEEE

Modeling the Tunnel Field-Effect Transistor Based on Different Tunneling Path Approaches

Abstract: In this paper, the effect of a choice of the tunneling path approach on electrical characteristics of the silicon tunnel field-effect transistor (TFET) is theoretically investigated with the ...